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ALINT PRO

ALINT-PRO™ is a design verification solution for RTL code written in VHDL, Verilog, and SystemVerilog, which is focused on verifying coding style and naming conventions, RTL and post-synthesis simulation mismatches, smooth and optimal synthesis, correct FSM descriptions, avoiding problems on further design stages, clocks and reset tree issues, CDC, RDC, DFT, and coding for portability and reuse. The solution performs static analysis based on RTL and SDC™ source files uncovering critical design issues early in the design cycle, which in turn reduces design signoff time dramatically. Running ALINT-PRO before the RTL simulation and logic synthesis phases prevents design issues spreading into the downstream stages of design flow and reduces the number of iterations required to finish the design.

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SPECIFIC BENEFITS

  • Unified Team-based Design Management maintains uniformity across local or remote teams
  • Configurable FPGA/EDA Flow Manager interfaces with 120+ vendors tools allows teams to remain on one platform throughout FPGA development
  • Quickly deploy designs by using Text, Schematic and State Machine
  • Distribute or deliver IPs using more secure and reliable Interoperable Encryption standard

  • Powerful common kernel mixed language simulator that supports VHDL, Verilog, SystemVerilog(Design) and SystemC
  • Ensure code quality and reliability using graphically interactive debugging and code quality tools
  • Perform metrics driven verification to identify unexercised parts of your design using Code Coverage analysis tools
  • Improve verification quality  and find more bugs using ABV - Assertion-Based Verification (SVA, PSL, OVA)
  • Connect the gap between HDL simulation and high level mathematical modeling environment for DSP blocks using MATLAB®/Simulink® interface

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