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Riviera PRO

Smart Planning for Smart Wireless Networks

Riviera-PRO™ addresses verification needs of engineers crafting tomorrow’s cutting-edge FPGA and SoC devices. Riviera-PRO enables the ultimate testbench productivity, reusability, and automation by combining the high-performance simulation engine, advanced debugging capabilities at different levels of abstraction, and support for the latest Language and Verification Library Standards.

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SPECIFIC BENEFITS

  • Unified Team-based Design Management maintains uniformity across local or remote teams
  • Configurable FPGA/EDA Flow Manager interfaces with 120+ vendors tools allows teams to remain on one platform throughout FPGA development
  • Quickly deploy designs by using Text, Schematic and State Machine
  • Distribute or deliver IPs using more secure and reliable Interoperable Encryption standard

  • Powerful common kernel mixed language simulator that supports VHDL, Verilog, SystemVerilog(Design) and SystemC
  • Ensure code quality and reliability using graphically interactive debugging and code quality tools
  • Perform metrics driven verification to identify unexercised parts of your design using Code Coverage analysis tools
  • Improve verification quality  and find more bugs using ABV - Assertion-Based Verification (SVA, PSL, OVA)
  • Connect the gap between HDL simulation and high level mathematical modeling environment for DSP blocks using MATLAB®/Simulink® interface

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